Multi-phase traffic control system

ABSTRACT

The control system includes multi-phase solid state traffic controllers for controlling the operation of traffic signals in accordance with traffic demand. These controllers include phase selection circuitry for directly transferring a go signal activation for one phase to a second phase for which a go signal is called for by a traffic detector without first allocating a go signal activation to another phase in which a traffic detector is not calling, i.e., is not traffic actuated. Circuitry is also provided for preempting the operation of a controller to allocate a particular preselected pattern of traffic signals. Also, circuitry is provided to ensure that after operating power has been lost and restored consistent traffic signals will be activated for all traffic phases.

United States Patent Hill et al.

[ 51 May 9,1972

[54] MULTI-PHASE TRAFFIC CONTROL SYSTEM [72] Inventors: Frank W. Hill,Moline, "1.; Peter G. Bartlett; Larry K. Clark, both of Davenport,

Iowa

[73] Assignee: Gulf & Western Industries, New York,

[22] Filed: Aug. 20, 1968 [2]] Appl. No.: 812,476

[52] U.S. Cl ..340/37 [51] Int. Cl. ..G08g 1/08 [58] Field of Search..340/3 1 37 [561 References Cited UNITED STATES PATENTS 3,508,1924/1970 Brockett ..340/37 FOUR PHASE FULL ACTUATED CONTROLLERAttorney-Meyer, Tilberry and Body 57 ABSTRACT The control systemincludes multi-phase solid state traffic controllers for controlling theoperation of traffic signals in accordance with traffic demand. Thesecontrollers include phase selection circuitry for directly transferringa go signal activation for one phase to a second phase for which a gosignal is called for by a traffic detector without first allocating a gosignal activation to another phase in which a traffic detector is notcalling, i.e., is not traffic actuated. Circuitry is also provided forpreempting the operation of a controller to allocate a particularpreselected pattern of traffic signals. Also, circuitry is provided toensure that after operating power has been lost and restored consistenttraffic signals will be activated for all trafiic phases.

19 Claims, 13 Drawing Figures ONE WAY STR E ET PATENTEUMY 9|9T2 SHEET 1OF 9 INVENTORS. HILL FOUR PHASE FULL ACTUATED CONTROLLER FRANK w.

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ATTORNEYS TC-2, ETC.

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ATTORNEYS FIG.4

PATENTEnm 9 1972 3,662,329

sum 5 r 9 P2 Pl 7 V ws f WAVE 0 [TO T OF FF-3 SHAPER llO PHASE SELECTll2 K||4 KHG LOGIC PSL NOR NOR}} NOF9 FROM SELECT SS STOP SSL cALL ONNOR OTHER g I I23 25 NOR NOR B-NOR Q} Y'-- I T TO c oE EF-s "0" OF FF 3L NOR NOR39 NOR)? FIG. 6 TO COF FF-4 CALL ON FROM OF FF-4 OTHER SIDE'NOR 142 AM i NOR BM TO FIG. 6 (I22) FROM "0" OF FF-4 NOR NOR

INVENTORS- FRANK w. HILL, FIG, 7 LARRY K. CLARK a BY PETER G.- BARTLETTMay, 711604 8 Bad,

I ATTORNEYS PATENTEUHAYQIWZ I 3,662,329

SHEET 6 [IF 9 7 PHASE ON LOGIC POL I90 I94 I FROM I60 NOR NOR d 5% T NORFRQMTBE ON I92 I96 202 c FROMJBO NOR NOR NOR (Dc ON 204 FROM I84 a \IQLNOR 5 NOR A 0N FROM I86 200 206 b NOR NOR DB ON FIG. 8 20B FROM "0" OFFF-3- V 7 5NE' XT' LEFT FROM "I" OF FF-3 NOR a) NEXT RIGHT 2'4 SELECTSTOP LOGIC SSL FROM "I" OF FF-4 NOR ID NEXT BARRIER RIGHT 2'6 FROM "0"OF FF-4 NOR (1) NEXT BARRIER I EI=T A ON u 1 226 234 OCB ON II NOR o ONLd 2|8 NOR I NOR 230 2380-7- 220 W 33 W NORT 232 240 Bram-1 224 NOR TSI;

INVENTORS. H6 9 FRANK w. HILL,

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ATTO RNEYS PATENTEDHM 9 I972 SHEET 7 [IF 9 NNNN 4 1 #mm @mm Ohm mO W iPO P INVENTORS. FRAN K W. HILL LARRY K. CLAFQK a v BYPETER e. BARTLETTMaya, 746% 8 flatly ATTORNEYS PATENTEDMAY 9 I972 SHEET 9 [IF 9 NOR NOR8+ 80. 55'; In (DON 0% INoR '80-] RIGHT 5+ 500 I I: 1 T0 I90 i L, I 852?s:

NoR NOR 5 NOR wen 1 58 504 d) ON --.m NTE 5+ T NOR NoR J 50s L 1 g L,LE'I-3!I'ER C -N0R l NoR o 33 g 508 IS 524 c f@ 4 j 807 GREEN E1" 5|O Li g 526 L- l YELLOW TNQR NOR NoR L 2 y ORIENTATION PROGRAMI NG FIG. l3

INVENTORS. FRANK w. HILL, LARRY K. CLARK a B PETER s. BARTLETT ATTORNEYSMULTI-PI-IASE TRAFFIC CONTROL SYSTEM The present invention relates tothe art of traffic control and, more particularly, to controllingtraffic flow in accordance with traffic demand. a

The invention is particularly applicable to the art of traffic controland will be described with particular reference thereto; although it isto be appreciated that the invention has broader applications, such asin process controls for controlling energization of a plurality ofloads.

Traffic controllers serve to control traffic signals which display go,caution, and stop signals to vehicles in thoroughfares representingtraffic phases allocated to movements of traffic in such thoroughfares.Pretimed traffic controllers serve to control such traffic signals on apretimed schedule. Actuated controllers, such as semi-actuatedcontrollers or full actuated controllers, control such traffic signalsin accordance with traffic demand as registered with the controllers bytraffic detectors. A full actuated traffic controller has a detectorassociated with each phase and a semi-actuated controller has a detectorassociated with at least one, but not all, of the phases served by thecontroller.

Many actuated traffic controllers serve to control traffic signals at anintersection of three or more traffic phases, such as phases A, B, andC. If the controller is allocating a go signal to phase A, and phase Cbecomes traffic actuated, i.e., its associated detector has beenactuated by a vehicle, then phase C is calling for allocation of a gosignal. Some of the older trafiic controllers would, in such a case asdiscussed, allocate a go signal to phase B, before allocating a gosignal to the calling phase C. Since phase B was not traffic actuated,such an allocation of go time to phase B is an unnecessary waste of gotime in a cycle of operation and may inhibit a smooth progressive flowof traffic through an intersection. A more efficient use of the trafficcontroller would be to directly transfer allocation of a go signal fromphase A to calling phase C, without first awarding go time to phase B.

A traffic control system known in the prior art provides a phaseselection circuit which serves, in the above example, to directlytransfer a go signal from phase A to phase C. That system proposes thata timing module be used foreach phase for controlling all timingoperations for the traffic signals for that phase. A phase selectcircuit couples the modules in such a manner that a module associatedwith an actuated traffic phase will be conditioned to commence timingoperations if it is the first so conditioned module in a seriesconnected circuit to receive a phase selection signal. Such a system,for example, is disclosed in the Arthur E. I-Iilliker U.S. Pat. No.3,191,148.

The present invention includes a traffic control system having animproved phase selection circuit for directly transferring a go signalactivation from one phase to a phase associated with a traffic detectorwhich has detected traffic. In accordance with this aspect of theinvention, it is contemplated that a traffic control system be providedwith signal light means for displaying traffic signals including a gosignal for each of at least three traffic phases, and wherein signalcontrol elements for at least two of the phases are trafiic actuatablehaving traffic detection means associated therewith for detectingtrafiic in thoroughfares associated with such actuatable phases.

In accordance with one aspect of the present invention, an improvementis provided and includes a common timer circuit associated with all ofthe phases and having go timing means for timing a go interval;actuatable timer control circuit means for each phase for, whenactuated, controlling the duration that the go timing means times a gointerval; and, phase selection means for actuating an actuatable timercontrol circuit means associated with an actuated one of the trafficphases, whereby the go signal display is directly transferred from oneof the phases to an actuated one of the phases.

In accordance with a still further aspect of the present invention, theimprovement comprises separate actuatable means for each phase for, uponactuation, controlling allocation of a go signal display to that phase;calling means for each actuatable phase for providing a calling signalrepresentative that the control for the associated phase is-trafiicactuated; actuatable phase selection counting means for counting triggerpulses obtained from a source of trigger pulses, with the counting meanshaving a plurality of output circuits which carry a pattern of outputsignals that changes in dependence upon the number of trigger-pulsescounted, and that this pattern of output signals is representative atany one time of condition in one of the phases; logic comparison meansfor comparing the pattern of output signals with the calling signals forproviding a comparison signal when the 'pattem of output signals isrepresentative of the same actuated phase that is represented by acalling signal; and, phase on actuating means for actuating the separateactuatable means associated with the same actuated phase so as tocontrol allocation of a go signal displayed thereto, whereby a go signaldisplay is directly transferred from one of the phases to an actuatedone of the phases.

In accordance with a still further aspect of the present invention,there is provided orientation programming means for actuating eachcalling means so that each of the calling means provides a callingsignal representative that its associated phase is traffic actuated.

In accordance with a still further object of the present invention,there is provided preemption control circuit means for actuating thephase on actuating means to, in turn, actuate a preselected one of theactuatable timer control circuit means.

The primary object of the present invention is to provide an improvedtraffic control system incorporating solid state components so as tothereby minimize maintenance and power requirements for economy ofoperation.

Another object of the present invention is to provide an improved solidstate multiphase traffic actuated controller.

A still further object of the present invention is to provide animproved phase select circuit for directly transferring allocation of gosignals from one phase to an actuated phase.

A still further object of the present invention is to provide animproved traffic controller having a preemption control circuit forpreempting the operation of the controller to allocate a particularpreselected pattern of traffic signals.

A still further object of the present invention is to provide animproved traffic controller having orientation programming circuit meansto ensure that after operating power has been lost and restored all ofthe traffic phases will be sequentially allocated traffic signals.

These and other objects and advantages of the invention will becomeapparent from the following description of the preferred embodiments ofthe invention as read in connection with the accompanying drawings inwhich:

FIG. 1 is a schematic illustration of the invention as applied to atraffic control system incorporating a four phase, full actuated trafficcontroller;

FIG. 2 is a combined schematic-block diagram illustration of the fourphase, full actuated traffic controller;

FIG. 3 is a schematic illustration of the timer circuit found withinFIG. 2;

FIG. 4 is a schematic illustration of load control circuitry coupled toFIG. 2;

FIG. 5 is a combined schematic block diagram illustrating the phaseselect circuitry in greater detail than that shown in FIG. 2;

FIG. 6 is a schematic illustration of the phase select logic circuitryshown in block diagram in FIG. 5;

FIG. 7 is a schematic illustration of the call on the other side logiccircuitry shown in block diagram in FIG. 5;

FIG. 8 is a schematic illustration of the phase on logic circuitryillustrated in block diagram in FIG. 5; 7

FIG. 9 is a schematic illustration of the select stop logic cir cuitryillustrated in block diagram in FIG. 5;

FIG. 10 is a combined schematic block diagram illustration of a secondembodiment of the invention;

FIG. 11 is a schematic illustration of circuitry used with theembodiment shown in FIG. 10;

FIG. 12 is a schematic illustration of preemption control circuitry;and,

FIG. 13 is a schematic illustration of orientation programmingcircuitry.

Referring now to the drawings, wherein the showings are for purposes ofillustrating the preferred embodiments of the invention and not for thepurposes of limiting same, FIG. 1 illustrates one application of theinvention as applied to a four phase, full actuated traffic controllerLC-l, which is more specifically illustrated in FIGS. 2 through 9. Thiscontroller serves to allocate and time go and caution signals to trafficphases A, B, C, and D. Each of these traffic phases is traffic actuated;to wit, each includes a traffic detector. Thus, phase A includesdetectors D1 and D2, phase B includes detectors D3 and D4, phase Cincludes detector D5, and phase D includes detectors D6 and D7. In oneform, each detector may be a spot detector, such as the familiar treadlepad which provides a momentary pulse each time a vehicle is detected.Al-

ternatively, the detectors may take the form of presence detectors whichmay be used in a counting operation for providing a pulse for eachdetected vehicle. It is also contemplated that the detectors may takethe form of true presence detectors which provide a presence signal solong as a vehicle is present within a zone of influence. Such presencedtectors may be eitherloop detectors or ultrasonic detectors, both ofwhich are well known to those skilled in the art.

LOCAL CONTROLLER GENERAL DESCRIPTION Reference is now made to FIG. 2,which is a combined schematic block diagram illustration of the localcontroller LC-l for controlling the operation of signal light S todisplay go and caution signals for each of the traffic phases A, B, D,and D. The local controller LC-l generally comprises: a common timercircuit T associated with all of the traffic phases and which includes ago timer T1, and a caution timer T2; a common traffic interval sequencercircuit IS; a phase A timer control circuit TC-l; a phase B timercontrol circuit TC-2; a phase C timer control circuit TC3 and a phase Dtimer control circuit TC-4; and, a phase on select circuit PS.

TIMER CONTROL CIRCUITS Timer control circuits TCl, TC-2, TC-3, and TC-4are substantially identical to each other and, accordingly, likecomponents are identified with like character references for simplifyingthe description of the invention. The description that follows is givenwith particular respect to timer control circuit TC1. As shown in FIG.2, timer control circuit TC-l includes an NPN-transistor having itscollector connected to a 8+ power supply source and its emitterconnected to a go timing potentiometer 12, andto a caution timingpotentiometer 14. As shown, these two potentiometers have theirresistance portions connected together in parallel between ground andthe emitter of transistor 10. The wiper arm of potentiometer 12 iscoupled through a diode l6, poled as shown, to timer circuit T1.Similarly, the wiper arm of potentiometer I4 is connected through adiode l8, poled as shown, to timer circuit T2. It will be noted thattimer control circuits TC-l through TC-4 are connected together inparallel and, in the event the controller serves to control more thanfour traffic phases, the additional timer control circuits will also beconnected in parallel with timer control circuits TC-l through TC-4.Briefly, whenever transistor 10 in timer control circuit TC-l isactuated into conduction, essentially B+ potential is applied across theresistance portions of potentiometers 12 and 14. The wiper arms on thesetwo potentiometers are adjusted, as desired, to provide voltages forapplication to timer circuits T1 and T2, which voltages respectivelycontrol the time duration that these two timers perform their timingfunctions.

COMMON TIMER CIRCUITS The common timer circuit T incorporates a go timerT1 and a caution timer T2, having their inputs respectively coupled tothe commonly connected outputs of go and caution timing potentiometersl2 and 14 in the timer control circuits TC-l through TC-4. In addition,another input to timer T1 and to timer T2 is obtained from an outputcircuit g of sequencer circuit lS'Another input to timer T1 is takenfrom an output circuit y of sequencer circuit IS.

Reference is now made to FIG. 3 which schematically illustrates timercircuits T1 and T2. As shown there, timer circuits T1 and T2 aresubstantially identical and, accordingly, like components are identifiedwith like reference numbers. The description which follows isspecifically given with reference to timer circuit T1. As shown, timercircuit Tl includes an NPN-transistor 20 having its base connected tooutput circuit y 'of sequencer IS and its emitter connected to ground.The collector to emitter circuit of transistor 20 is connected inparallel with a timing capacitor 22. The junction of the collector oftransistor 20 and one side of capacitor 22 is connected through a timingresistor 24 to a 8+ voltage supply source. Capacitor 22 is coupled to acomparator circuit in the fonn of a differential amplifier, includingNPNtransistors 26 and 28, having their emitters connected together incommon and thence through a resistor 30 to ground. The collectors oftransistor 26 and transistor 28 are respectively connected throughresistors 32 and 34 to the B+ voltage supply source. The base oftransistor 28 is connected to the commonly connected cathodes of diodes16 in timer control circuits TC-1 through TC-4. The collector oftransistor 28 is connected to the input of a timer memory circuit TM.This timer memory circuit includes two NOR-gates 36 and 38 connectedtogether to define a two input, bistable multivibrator circuit. Oneinput to the timer memory circuit is taken from the collector oftransistor 28 and is applied to the input of NOR-gate 36. The secondinput to the timer memory circuit TM is taken from output circuit 8 ofsequencer IS, through a capacitor 40, and thence to one input ofNOR-gate 38. The output of N OR-gate 38 serves as the output of thetimer memory circuit TM and is applied (as shown in FIG. 2) to an inputterminal T1 of the phase select circuit PS, as well as to one input ofan AND-gate 42.

Timer circuit T2 differs from timer circuit Tl only inasmuch as the baseof transistor 20 is connected to the output circuit g of sequencercircuit IS and that the base of transistor 28 is connected to thecommonly connected cathodes of diodes 18 in the timer control circuitTC-l. through TC-4. Also, the output of NOR-gate 38 in timer circuit T2isconnected (as shown in FIG. 2) to terminal T2 of phase select circuitPS as well as to the interval sequencer circuit IS.

DETECTOR MEMORY CIRCUITS Reference is now made to FIG. 2, whichillustrates detector memory circuits AM, BM, CM, and DM, which arerespectively associated with phases A, B, C, and D for rememberingtraffic actuations taking place in those phases. Detector memory circuitAM includes a pair of NOR-gates 44 and 46 connected together to define atwo input bistable multivibrator circuit. The input to NOR-gate 44 istaken from the output of a NOR-gate 48, having its input connectedthrough a resistor 50 to a B+ voltage supply source. The input to NOR-gate 48 is also connected through a normally open switch DA to ground.Switch DA is a simplified showing of detectors D1 and D2 associated withphase A and serves, when a vehicle is detected in phase A, to becomeclosed to apply a ground potential or binary 0 signal to the input ofNOR-gate 48.

In a manner similar to that as described above, the detector memory BMincludes NOR-gates 52 and 54 connected together to define a bistablemultivibrator circuit. NOR-gate 56 is connected to the input of NOR-gate52. The input to NOR-gate 56 is taken through a resistor 58 to the B+voltage supply source as well as through a normally open switch DB,representative of phase B traffic detectors D3 and D4.

Detector memory CM takes the form of a pair of N OR-gates 60 and 62connected together to define a bistable multivibrator circuit. The inputto NOR-gate 60 is taken from the output of a NOR-gate 64 having itsinput connected through a resistor 66 to a B+ voltage supply source, aswell as through a normally open switch DC to ground. Normally openswitch DC is a simplified illustration of detector D5 associated with aphase C.

Detector memory DM includes a pair of NOR-gates 68 and 70 connectedtogether to define a bistable multivibrator circuit. The input toNOR-gate 70 is taken from the output of a NOR-gate 72 having its inputconnected through a resistor 74 to a B+ voltage supply source as well asthrough a normally open switch DD to ground. Normally open switch DD isa simplified illustration of phase D detectors D6 and D7.

The outputs of NOR-gates 46, 54, 62, and 68 are respectively coupled toinput terminals AM, BM, CM, and DM in the phase select circuit PS. Also,the phase select circuit PS has four output circuits a, b, c, and dwhich are respectively coupled to the inputs of NOR-gates 46, 54, 62,and 68.

INTERVAL SEQUENCER CIRCUIT The inverval sequencer circuit IS serves tocontrol the sequence of the intervals to be allocated and timed for eachtraffic phase. Thus, within any particular phase, the sequencer servesto ensure that when, for example, the phase A operation commences, thetimer T1 completes its timing function before timer T2 commences itstiming function. The sequencer circuit IS may take various forms and, asshown in FIG. 2, it includes two NOR-gates 80 and 82 connected togetherto define a two input bistable multivibrator circuit. One input toNOR-gate 80 is taken from the output of AND- gate 42. Also, one input ofN OR-gate 82 is taken directly from the output of NOR-gate 38 in thecaution timer circuit T2. The output of NOR-gate 80 is connected to anoutput circuit g. Similarly, the output of NOR-gate 82 is connected tooutput circuit y.

SIGNAL LIGHT CONTROL CIRCUITS Reference is now made to FIG. 4 whichillustrates a signal light control circuit to be used for energizing go,caution, and stop signal lights associated, for example, with phase A.This circuit is described with respect to phase A; however, it should beappreciated that a similar circuit may be used for phases B, C, and D.As shown in FIG. 4, the control circuit serves to energize the phase Agreen light AG, or the phase A yellow light AY, or the phase A red lightAR. The circuit includes NOR-gates 90, 92, and 94 having their inputsrespectively coupled to output circuit a of the phase select circuit PSand to output circuits g and y of the interval sequencer circuit IS. Thetwo inputs of NOR-gate 94 are respectively connected to the outputs ofNOR-gates 90 and 92. The inputs of NOR-gate 98 are respectivelyconnected to the outputs of NOR-gates 90 and 94. The output of NOR-gates96 and 98 are coupled to the inputs of a NOR-gate 100. Also, the outputsof NOR-gates 96, 98, and 100 are respectivelycoupled to load switchesLS-l, LS-2 and LS-3. These load switches may, for example, take the formof triacs having their gates connected to the outputs of the associatedNOR-gates 96, 98, and 100. As is well known, once a positive signal isapplied to the gate of such a triac, the triac is gated into conductionfor purposes of switching an alternating current voltage source across aload. Alternating load current source V is coupled to each of the loadswitches LS-l, LS-2, LS-3 which, when gated into conduction by theirrespective NOR gates, serve to couple the voltage source across theselected signal light AG, AY, or AR.

GENERAL OPERATION OF CONTROLLER Before describing the specific circuitryof the phase select circuit PS shown in block diagram form in FIG. 5 andin greater detail in FIGS. 6, 7, 8, and 9, a description of theoperation of the local controller LC-l described thus far is presented.Briefly, whenever a right-of-way signal is allocated to a particularphase, such as phase A, the common go timer T1 is actuated to time aperiod of time as adjusted by potentiometer 12 in the timer controlcircuit TC-1. Once timer T] has completed-its timing function, the phaseselect circuit PS serves to determine whether any of the other phasesare traffic actuated; to wit, whether any of the detectors associatedwith traffic phases B, C, and D has detected a vehicle. Once thisdetermination has been made, an output signal is placed on select stopterminal SS (see FIG. 2). Since timer circuit Tl has timed out and apositive signal is obtained from select stop terminal SS, a binary 1"signal is obtained from the output of AND-gate 42. Depending upon whichphase B, C, or D is selected, output circuits b, c, or d will beenergized to carry a positive signal; to wit, a binary l signal.

In operation of the controller it may be assumed that output circuit aof phase select circuit PS is energized to provide a phase on signal.This is a positive or binary l signal which serves to forward biastransistor 10 in timer controlcircuit TC1 into conduction. Thus,potentiometers l2 and 14 in timer control circuit TC-l apply controlpotentials to timer circuits T1 and T2 in the common timer T. During theprevious traffic interval the output circuit of sequencer circuit ISprovided a positive potential to forward bias transistor 20 (see FIG. 3)into conduction to short circuit timing capacitor 22 in timer circuitT1. However, when timer circuit T2, during that previous interval,completed its timing function the output circuit y, which is connectedto the output of NOR-gate 82, became a binary 0" signal or groundpotential, therefore removing this short circuit. Accordingly, duringthe phase A operation timer circuit Tl commences to time by permittingcapacitor 22 to charge toward the B+ potential. Since the base oftransistor 28 is coupled to potentiometer 12 in timer control circuitTC-l, a potential as determined by the adjustment of the wiper arm ofpotentiometer 12 is applied between ground and the base of transistor28. When the voltage stored by capacitor 22 exceeds that applied betweenground and the base of transistor 28, transistor 28 will be reversebiased and a positive, i.e., a binary l," signal is applied to the inputof NOR-gate 36 in the timer memory circuit TM. Thus, the output ofNOR-gate 36 becomes a binary 0 signal, causing the output of NOR-gate 38to become a binary l signal. This binary 1 signal is applied to terminalT1 in the phase select circuit PS, as well as to one input of AND-gate42. The phase select circuit now commences its phase selection operationand once it has determined which phase, B, C, or D, will next beallocated a right-of-way signal, the select stop circuit SS is energizedto apply a second binary l signal to the input of AND-gate 42.Accordingly, AND-gate 42 now applies a binary l signal to the input ofNOR-gate in the interval sequencer circuit IS. This forces the output ofNOR-gate 80 to be changed to a binary "0 level, deenergizing outputcircuit g. Also, the output of NOR-gate 82 now carries a binary lsignal, energizing output circuit y.

Referring now to FIG. 3 since output circuit y is energized to carry abinary l signal, transistor 20 in timer circuit T1 is forward biased tomaintain that timer reset by short circuiting capacitor 22. Since outputcircuit g is now deenergized, the short circuit is removed fromtransistor 20 in timer circuit T2. Accordingly, timer circuit T2operates in the same fashion as described above with respect to timercircuit T1 and once the circuit has completed its timing function, itprovides a binary 1 signal at the output of NOR-gate 38 in timer circuitT2 and this signal is applied to terminal T2 in the phase select circuitPS, as well as to one input of NOR-gate 82 in the interval sequencercircuit IS. Application of this binary l signal to the input of NOR-gate82 causes the sequencer circuit IS to revert to its original condition,wherein the output terminal 3 is energized and the output terminal y isdeenergized.

During the phase A operation, described above, the output circuit a ofthe phase select circuit PS is energized and at different times outputcircuits g and y of the sequencer circuit IS are energized. Reference isnow made to FIG. 4 from which it will be noted that during the periodthat output circuits a and g are both energized, the outputs ofNOR-gates and 92 carry binary signals, whereupon the output of NOR-gate96 applies a positive or binary l signal to trigger load switch LS-linto conduction so that the alternating current voltage source V isapplied to energize the phase A green light AG. When the output g ofsequencer circuit IS is deenergized, light AG is deenergized. Whensequencer output circuit y becomes energized during the period thatoutput circuit a is energized, then the output of NOR-gate 98 carries abinary 1 signal for actuating load switch LS-2 into conduction toenergize the phase A yellow light AY. Whenever terminals g and y areboth deenergized, or whenever either of these are energized, but outputcircuit a of the phase select circuit is not energized, then NOR-gates96 and 98 carry binary 0 signals, causing NOR-gate 100 to apply a binary1 signal to actuate load switch LS-3 into conduction to energize thephase A red light AR.

Having now provided a description of the operation of local controllerLC-l, attention is specifically directed to the phase select circuit PSshown in FIGS. 5 through 9.

PHASE SELECT CIRCUIT Reference is now made to FIG. 5, which presents acombined schematic block diagram illustration of the phase selectioncircuit PS shown as a single block diagram in FIG. 2. As shown in FIG.5, the phase select circuit generally comprises a phase select logiccircuit PSL; a call on the other side logic circuit COS; a phase selectsearch circuit PSS, including a phase next ring flip-flop FF-3 and aphase next barrier flip-flop FF-4; a shift logic circuit SL; a phase onnext flip-flop FF-S; a phase on next barrier flip-flop FF-6; a phase onlogic circuit POL and a select stop logic circuit SSL. Circuits PSL,COS, POL, and SSL are illustrated in greater detail in FIGS. 6, 7, 8,and 9, respectively.

PHASE SELECT LOGIC CIRCUIT Referring now to FIG. 6, the phase selectlogic circuit PSL includes an alternating current voltage source Vcoupled between ground and a wave shaper WS, having its output circuitconnected to ground through a diode 110, poled as shown, so as toprovide a plurality of positive trigger pulses Pl P2, etc., which areshaped as square waves of the same amplitude and duration and are of afixed frequency, such as one pulse per second. The output of wave shaperWS is applied to trigger terminal T of flip-flop FF-3 in the phaseselect search circuit PSS (FIG. 5). Input terminal T1 of the phaseselect logic circuit PSL is connected to the input of a NOR-gate 112having its output connected to the input of a NOR-gate 114. A secondinput to NOR-gate 114 is taken from the select stop terminal SS of theselect stop logic circuit (FIG. 9). The output of NOR-gate 114 iscoupled through a NOR-gate 116 to the input of a NOR-gate 1 18. A secondinput to NOR-gate 118 is taken from the 0" output terminal of flip-flopFF-3 in the phase select search circuit PS8. The output of NOR-gate 118is applied as one input to a NOR-gate 120. The second input to NOR-gate120 is taken from the 0" terminal of flip-flop FF-3, and a third inputto NOR-gate 120 is taken from the input terminal y. NOR-gate 122 has itsinput connected through a resistor 124 to ground, as well as to theoutput of the call on other side logic circuit COS (FIG. 7). The outputof NOR gate 122 is applied as a fourth input to NOR-gate 120. The outputof NOR-gate 120 is applied as one input to a NOR- gate 123,having asecond input taken from the output of NOR-gate 116. The output ofNOR-gate 123 is taken through NOR-gate 125 to terminal C of flip-flopFF-3 in the phase select search circuit PS5. The output of NOR-gate 118is applied to the input of a N OR-gate 126. The output of NOR-gate 126in turn is applied to the input of a NOR-gate 128 having a second inputtaken from the output of NOR-gate 122. The output of NOR-gate 128 isapplied through a NOR-gate 130 to terminal c of flip-flop FF-4 in thephase select search circuit PS8.

8 CALL ON OTHER SIDE LOGIC Reference is now made to FIG. 7 whichschematically illustrates the call on other side logic circuit COS whichis shown in block diagram form in FIG. 5. This circuit includes a pairof NOR-gates and 142. NOR-gate 140 has its input connected to terminal lof flip-flop FF-4 in phase select search circuit PSS. NOR-gate 142 hastwo inputs, one taken from the input terminal AM and the other takenfrom the input terminal BM. The outputs of NOR-gates 140 and 142 areconnected to the inputs of a NOR-gate 144 having its output connectedthrough a diode 146, poled as shown. The circuit also includes a secondpair of NOR-gates 148 and 150. NOR-gate 148 has its input taken fromoutput terminal "0 of flip-flop FF-4 in phase select search circuit PSS.NOR-gate 150 has two inputs respectively taken from input terminals CMand DM. The outputs of NOR-gates 148 and 150 are connected as the inputsto a NOR-gate 152 having its output connected through a diode 154, poledas shown, Diodes 146 and 154 are connected together, as shown, with theoutput of the circuit connected to the input of NOR-gate 122 in thephase select logic circuit shown in FIG. 6.

PHASE SELECT SEARCH CIRCUIT PSS Referring now to FIG. 5, the phaseselect search circuit PSS includes a phase next ring flip-flop FF-3 anda phase next barrier flip-flop FF-4. The internal circuitry of eachflip-flop does 790?, or the equivalent. Conventionally, such a flip-flopis labeled with output terminals l 0 for the two stable states of theflip-flop, together with a label S for the set input terminal, label Cfor the clear input terminal, and label T for the trigger inputterminal. As shown, the set S and clear C terminals of each flip-flopare connected together in common. The common connection for flip-flopFF-3 is connected to the output of NOR-gate 125 in the phase selectlogic circuit PSL. Similarly, the common connection of flip-flop FF-4 isconnected to the output of N OR-gate 130 of the phase select logiccircuit PSL. The input trigger terminal T of flip-flop FF3 is connectedto the output of wave shaper WS in the phase select logic circuit PSL.Upon receipt of the trailing negative going edge of pulses P1, P2, etc.,taken from the output of wave shaper WS, flip-flop FF-3 changes from onestable state to the other. Output terminal 1 of flip-flop FF-3 isconnected to the input trigger terminal T of flip-flop F F-4.

SHIFT LOGIC CIRCUIT Reference is now made to FIG. 5 which illustratesthe shift logic circuit SL. As shown in FIG. 5, the circuit includesNOR- gates 160, 162, 164, 166, 168. Each of these NOR gates has oneinput connected to the output of a NOR-gate having its input connectedto input terminal T2. The output of NOR- gate 160 is connected to oneinput of the phase on logic circuit POL. A second input of NOR-gate 162is taken from output terminal 1 of flip-flop FF-3 and the output of thisNOR gate is connected to the phase on next flip-flop FF-S. A secondinput of NOR-gate 164 is connected to output terminal 0 of flip-flopFF-3 and the output of this NOR gate is connected to the phase on nextflip-flop FF-S. One input of NOR-gate 166 is connected to outputterminal l of flip-flop FF-4 and the output of this NOR gate isconnected to the phase on barrier flip-flop FF-6. Similarly, one inputof NOR-gate 168 is connected to output terminal 0 of flip-flop FF-4 andthe output of this NOR gate is connected to the phase on barrierflip-flop F F-6.,

FLlP-FLOPS F F-S, F F-6 As shown in FIG. 5, the phase on next flip-flopFF-5 includes a pair of NOR-gates and 182 connected together to define atwo input bistable multivibrator circuit. The input to NOR-gate 180 istaken from the output of NOR-gate 162 and the input to NOR-gate 182 istaken from the output of NOR- gate 164. The outputs of NOR-gates 180 and182 are connected to the phase on logic circuit POL. The phase onbarrier flip-flop FF-6 is similar to flip-flop FF- and includes a pairof NOR-gates 184 and 186 connected together to define a two inputbistable multivibrator circuit. The input to NOR-gate 184 is taken fromthe output of NOR-gate 166 and the input to NOR-gate 186 is taken fromthe output of NOR-gate 168. The outputs of NOR-gates 184 and 186 areconnected to the phase on logic circuit POL.

PHASE ON LOGIC Reference is now made to FIG. 8 which provides aschematic illustration of the phase on logic circuit POL. As shown inFIG. 8, this circuit includes a pair of NOR-gates 190 and 192. NOR-gate190 has two inputs, one being connected to the output of NOR-gate 160 inthe shift logic circuit SL, and the other being connected to the outputof NOR-gate 182 in flip-flop FF-S. Similarly, NOR-gate 192 has twoinputs, one being connected to the output of NOR-gate 160 and the otherbeing connected to the output of NOR-gate 180 in flip-flop FF-S. Theoutputs of NOR-gates 190 and 192 are connected to the inputs ofNOR-gates 194 and 196, respectively. NOR- gates 198 and 200 have theirinputs respectively connected to the outputs of NOR-gates 184 and 186 inthe phase on barrier flip-flop FF-G. NOR-gate 202 has two inputs, onebeing taken from the output of NOR-gate 194 and the other being takenfrom the output of NOR-gate 198. Similarly, NOR-gate 204 has two inputs,one being taken from the output of NOR-gate 196 and the other beingtaken from the output of NOR-gate 198. NOR-gate 206 has one input takenfrom the output of NOR-gate 196 and the other input taken from theoutput of NOR-gate 200. Also, NOR-gate 208 has one input taken from theoutput of NOR-gate 194 and the other being taken from the output ofNOR-gate 200. The outputs of NOR-gates 206, 208, 204, and 202 arerespectively connected to output terminals a, b, c, and d of the phaseselection circuit (see FIG. 2).

SELECT STOP LOGIC The select stop logic circuit is more particularlyillustrated in FIG. 9, and includes four NOR-gates 210, 212, 214, and216. The inputs to NOR-gates 210 and 212 are respectively taken from thel and 0 output terminals of flip-flop FF-3. Similarly, the inputs toNOR-gates 214 and 216 are respectively taken from the l and 0 outputs offlip-flop FF-4. The select stop logic circuit also includes NOR-gates218, 220, 222, and 224 having their inputs respectively connected toterminals AM, BM, CM and DM'. The circuitry also includes NOR-gates 226,228, 230, and 232. NOR-gate 226 has four inputs respectively taken fromoutput terminal a, the output of NOR-gate 210, the output of NOR-gate216 and the output of NOR-gate 218. Similarly, NOR-gate 228 has fourinputs respectively taken from output terminal 11, the output ofNOR-gate 212, the output of NOR-gate 216, and the output of NOR-gate220. Also, NOR-gate 230 has four inputs respectively taken from outputcircuit c, the output of NOR-gate 210, the output of NOR-gate 214 andthe output of NOR-gate 222. Further, NOR-gate 232 has four inputsrespectively taken from the output circuit d, the output of NOR-gate212, the output of NOR-gate 214, and the output of NOR-gate 224. Theoutputs of NOR-gates 226, 228, 230, and 232 are respectively connectedthrough diodes 234, 236, 238, and 240 and thence connected together incommon to output terminal SS.

PHASE SELECTION GENERAL DESCRIPTION The following is a generalizeddescription of the phase selection operation with reference to FIGS. 2and 5. This description is given in a functional manner and a moredetailed description will follow with reference to FIGS. 6, 7, 8, and 9.

Once a phase has been selected to which control of allocation of aright-of-way signal will be transferred, this information is shifted bymeans of the shift logic circuit SL to the flipflops FF5 and FF-6. Thisinformation, in turn, is decoded by the phase on logic circuit POL andone of its outputs a, b, c, or d will be energized in accordance withwhich phase is to receive the control of allocation of a right-of-wayinterval.

The phase selection itself is accomplished by the phase select logiccircuit PSL working in conjunction with the phase select search circuitPS8. The flip-flops FF-3 and FF-4 in phase select search circuit PSSreceive input information from the phase select logic circuit PSL. Whenone of the detector memories AM, BM, CM, or DM (FIG. 2), is actuated,this condition is decoded by the call on other side logic circuit COS toprovide an output or calling signal to the phase select logic circuitPSL. This information, together with the information taken at inputterminals Tl, Y1, and from the select stop logic circuit SL, are decodedby phase select logic circuit PSL to actuate the phase select searchcircuit PSS. Once the searching function has beencompleted this is notedby the select stop logic circuit SSL whichsends a command back to thephase select logic circuit PSL to stop further searching operations.

A portion of the theory of operation involves a discussion of the termknown as Barrier. Traffic phases A and B will be considered as thephases on the left side of the barrier, and traffic phases C and D willbe considered as the phases on the right side of the barrier. Each sideof the barrier, in turn, has left and right sides. 0n the left side ofthe barrier phases A and B are respectively the left and right sides. Onthe right side of the barrier phases C and D are respectively the leftand right sides. If controller LC-l is displaying a right-of-way signalto phase A and the controller determines that phase B desiresright-of-way, then the operation which ensues takes place on the sameside of the barrier. If a detector call indicated that phase D (on theopposite side of barrier) is traffic actuated, then the phase nextbarrier flip-flop FF 4 will perform a portion of the phase select searchoperation.

Once the correct phase has been determined further searching is stoppedby the select stop logic circuit SSL. The information is then held untilthe yellow timer T2 completes its timing function. At that point, theshift logic circuit SL is actuated so that the information in the phaseselect search circuit PSS is shifted from flip-flops FF-3 and FF-4 toflip-flops FF5 and FF-6. The outputs of these flip-flops contain thecorrect information as to which phase should be allocated the nextright-of-way interval. This information is decoded by the phase on logiccircuit POL to energize the appropriate phase on terminal a, b, c, or d.

SAME SIDE OF BARRIER OPERATION Itmay be assumed that phase A is beingallocated a right-ofway signal and that a traffic actuation has takenplace in phase B. Also, it may be assumed that after phase A has beenallocated a right-of-way signal, timer Tl has completed its timingfunction and has provided a binary 1 output signal to input terminal T1of the phase select circuit as well as to one input of AND-gate 42.Since phase B is traffic actuated, normally open switch DB was at leastmomentarily closed. The momentary closure applied a binary 0 signal tothe input of NOR-gate 56 (FIG. 2). Accordingly, NOR-gate 56 applied abinary 1 signal to the input of detector memory BM, the output of whichapplies a binary l signal to terminal BM of the phase select circuit.

Referring now to FIGS. 5 and 7, it will be noted that the call on otherside circuit receives a binary 1" signal at its input terminal BM.Accordingly, the output of NOR-gate 142 applies a binary 0 signal to theinput of NOR-gate 144. A second input'to NOR-gate 144 is taken from theoutput of NOR-gate 140. The input to NOR-gate is taken from outputterminal 1 of flip-flop FF4. During operation on the left side of thebarrier, which involves phases A and B, output terminal l of flip-flopFF4 carries a binary signal. Accordingly, the output of NOR-gate 140 isa binary 1 signal. Thus, the output of NOR-gate 144 carries a binary 0signal.

Since during this operation, the 0 terminal of flip-flop FF-4 carries abinary l output signal, the output of NOR- gate 148 is a binary 0signal. Since no traffic has been detected in phases C and D, inputterminals CM and DM' carry binary "0 signals. Thus, NOR-gate 150 appliesa binary l signal to the input of NOR-gate 152. Since the outputcircuits of NOR-gates 144 and 152 carry binary 0" signals, a binary 0"signal is applied to the input of NOR-gate 122 in the phase select logiccircuit (FIG. 6).

The output circuit of NOR gate 122 applies a binary 1 signal to theinput of NOR-gate 120, as well as to the input of NOR-gate 128. Thus,the output of NOR-gate 128 carries a binary 0 signal causing the outputof NOR-gate 130 to apply a binary l signal to the clear terminal C offlip-flop FF-4 to hold that flip-flop from being actuated from onestable state to the other.

When timer T1 completes its timing function, it applies a binary 1signal to input terminal T1 of the phase select circuit PS. Accordingly,NOR-gate 112 in the phase select logic circuit PSL receives a binary lsignal at its input circuit, whereupon its output circuit applies abinary 0 signal to the input of NOR-gate 114. Since searching operationshave not been completed, a binary 0" signal is present on the selectstop terminal SS. Thus, NOR-gate 114 applies a binary l" signal toNOR-gate 116, the output of which applies a binary 0 signal to one inputof NOR-gate 123. Since, as stated hereinbefore, a binary l signal isapplied from the output of NOR-gate 122 to the input of NOR-gate 120, asecond binary 0 signal is applied to the second input of NOR-gate 123.Thus, NOR-gate 123 applies a binary l signal to the input of NOR-gate125. The output of NOR-gate 125, in turn, now applies a binary 0" signalto the clear terminal C of flip-flop FF-3 to permit that flip-flop to beactuated from one stable state to the other upon receipt of the trailingedge of the first pulse at its input trigger terminal T from wave shaperWS.

With a binary 0 signal being applied to terminal C of flipflop FF-3, thestrobe signal, i.e., the negative going trailing edge of the firstreceived pulse from wave shaper WS, serves to trigger the flip-flop fromone stable state to the other. If as assumed, the controller wasallocating a right-of-way signal to phase A, then a binary 1" signal iscarried by the 0 terminal of flip-flop FI -3. Accordingly, upon receiptof the first trigger pulse, the flip-flop FF-3 is actuated so that onlyits l terminal carries a binary l signal. This binary l signal isapplied to the select stop logic circuit 881. which will determine by acomparison with the outputs of detector memories AM, BM, CM, and DM ifthis count condition of flip-flop FF-3 corresponds with a trafficactuation having occurred in phase B. If so, further searching will beterminated.

Reference is now made to FIG. 9. Since phase B is traffic actuated, abinary 1 signal is present on input terminal BM whereupon NOR-gate 220applies a binary 0 signal to one input of NOR-gate 228. Since aright-of-way signal is being applied to phase A, and not to phase B,then output terminal b of the phase select circuit PS should carry abinary 0 signal. This binary 0 signal is applied to second input ofNOR-gate 228. The output terminal l of flip-flop F'F-B carries a binary1" signal which is converted by NOR-gate 212 to a binary "0 signal,which is then applied to a third input of NOR-gate 228. Also, the 0terminal of flip-flop FF-4 carries a binary l signal which is invertedby NOR'gate 216 so as to apply a binary 0" signal to the fourth input ofNOR-gate 228. Since all four inputs of NOR-gate 228 carry binary 0signals, the output of this NOR-gate applies a binary 1" signal throughdiode 236 to output terminal SS.

Reference is now made to FIG. 6, from which it will be noted that thebinary 1" signal at tenninal SS is applied to the input of NOR-gate 114so that this gate applies a binary 0 signal to the input of NOR-gate116. The output of NOR-gate 116 in turn applies a binary l signal to theinput of NOR- gate 123 so that the output of this NOR gate-now carries abinary 0" signal. Thus, the output of NOR-gate 125 will now carry abinary l signal which is applied to clear terminal C of flip-flop FF-3to prevent further trigger pulses from wave shaper WS from triggeringthis flipflop.

.Reference is now made to FIG. 2, from which it will be noted that whenthe select stop terminal SS carries a binary l signal, this signal isapplied to the second of two inputs of AND-gate 42. Timer circuit T1 hadpreviously timed out and, hence, both inputs of AND-gate 42 carry binaryl signals, whereupon the AND gate applies a binary 1" signal to oneinput of NOR-gate 80 in the interval sequencer circuit IS. This causesoutput circuit 3 to be deenergized to carry a binary "0" signal andoutput circuit y to carry a binary 1" signal. As discussed previouslywith respect to the description of operation of the timer circuits T1and T2, once the output terminal y becomes energized, the caution timerT2 is actuated so as to time a predetermined period of time as adjustedby the potentiometer 14 in timer control circuit TC-l. Once thetimingfunction has been completed, timer T2 applies a binary 1" signalto input terminal T2 of the phase select circuit.

Reference is now made to FIG. 5, from which it will be noted that oncetimer T2 has applied a binary l signal to input terminal T2, NOR-gate170 applies a binary 0 signal to one input each of NOR-gates 160, 162,164, 166, and 168. Since the phase select search circuit completed itssearching function after one pulse had been received from wave shaperWS, the output terminal l offlip-flop FF-3 now carries a binary 1"signal and the output terminal 0 now carries a binary 0 signal. Thecondition of the phase next barrier flipflop FF-4 has not changed, andhence its output terminal l still carries a binary 0 signal and itsoutput terminal 0" still carries a binary 1" signal. Since a binary 1"signal is now applied to one of its inputs, NOR-gate 162 applies abinary 0 signal to the input of NOR-gate 180 in flip-flop FF-S. Sinceboth of its inputs carry binary 0" signals, NOR-gate 164 applies abinary l signal to the input of NOR-gate 182. Through regenerativeaction, the output of NOR-gate 182 will now carry a binary 0 signal andthe output of NOR-gate 180 will now carry a binary l signal. Since oneof its inputs carries a binary 1 signal, the output of NOR-gate 168carries a binary 0 signal which is applied to one input of NOR-gate 186in flip-flop FF-6. Since both of its inputs carry binary 0" signals,NOR-gate 166 applies a binary l signal to the input of NOR-gate 184.Through regenerative action, the output of gate 186 now carries a binary1 signal, and the output of NOR-gate 184 now carries a binary 0 signal.

When timer T2 completes its timing function it applies a binary l signalto the input of NOR-gate 82 in the interval sequencer circuit IS. Thiscauses output circuit y to carry a binary 0 signal and output circuit gto carry a binary l signal. Since output circuit 8 now carries a binary1 signal, this resets timer memories TM in timer circuits T1 and T2(FIG. 3) whereupon the NOR-gates 38 in each of these two circuits carrybinary 0 signals. Thus, timer T2 now applies a binary 0" signal to inputterminal T2 of the phase select circuit PS.

Referring now to FIG. 5, since a binary 0" signal is now applied to theinput of NOR-gate 170, this NOR gate applies a binary 1 signal to oneinput each of NOR-gates 160, 162, 164, 166, and 168. Accordingly,NOR-gate now applies a binary 0 signal to the phase on logic circuitPOL. Since both of its inputs now receive a binary l signal, NOR-gate162 is unchanged and still applies a binary 0" signal to the input ofNOR-gate 180. However, since one of its inputs now receives a binary lsignal, NOR-gate 164 now applies a binary 0 signal to the input ofNOR-gate 182. This, however, does not change the status of thisflip-flop and NOR-gate and NOR-gate 182 still apply binary 1 and binary0" signals, respectively, to the phase on logic circuit POL. Since bothof its inputs now receive binary l" signals, NOR-gate 168 is unchangedand still applies a binary 0 signal to NOR- gate 186 in flip-flop FF-6.However, since one of its inputs now receives a binary l signal,NOR-gate 166 now applies a binary O signal to the input of NOR-gate 184.This, however, does not change the stable state of flip-flop FF-6 andits NOR-gates 184 and 186, respectively, apply binary and binary 1"signals to the input of the phase on logic circuit POL.

Reference is now made to FIG. 8. NOR-gate 190 now receives binary 0signals from the outputs of NOR-gates 160 and 182. Accordingly, NOR-gate190 applies a binary 1" signal to the input of NOR-gate 194, which, inturn, applies a binary 0 signal to one input of NOR-gate 208. Since NOR-gate 200 receives a binary 1 signal from NOR-gate 186, NOR-gate 200applies a binary 0 signal to the second input of NOR-gate 208. Sinceboth of its inputs receive binary 0" signals, NOR-gate 208 applies abinary 1 signal to output circuit b representative that phase b has beenselected to be the phase that next receives a right-of-way signal.

NOR-gate 202 receives a binary 1 signal from the output of NOR-gate 198and, accordingly, output circuit d is deenergized with a binary 0signal. NOR-gate 204 also receives a binary 1" signal from the output ofNOR-gate 198 and, accordingly, output circuit 0 is deenergized to carrya binary 0 signal. NOR-gate 206 receives a binary l signal from NOR-gate 196 and accordingly, output circuit a is now deenergized to carry abinary 0 signal. Since only output circuit b carries a binary 1 signal,the transistor in timer control circuit TC-2 is now actuated intoconduction so that go timer Tl now times a predetermined period of timeas adjusted by potentiometer 12 in timer control circuit TC-2 to controlthe time duration of the initial allocation of go time to phase B. Asdiscussed hereinbefore with reference to the operation for phase A, thisgo signal display will continue unless some other phase is trafficactuated. If so, since a binary 1" signal is applied to terminal T1 upontime out of timer T1, the phase select circuit will commence a searchingoperation to determine which phase is traffic actuated.

CROSSING TI-IE BARRIER In the previous description the phase selectionoperation took place on the same side of the barrier, and hence thephase selection search process terminated when the select stop logiccircuit SSL noted that phase B had been traffic actuated and had placeda calling signal. The description which follows will take place on theassumption that the calling phase was phase D and not phase B.

Since it is phase D that is traffic actuated and not phase B,

as discussed above, a binary signal is applied to input terminal DM ofthe call on other side logic circuit COS (FIG. 7). Thus, NOR-gate 150applies a binary 0 signal to one input of NOR-gate 152. Output terminal0 of the phase next barrier flip-flop FF-4 (FIG. 5) carries a binary 1signal since we are still operating on the left side of the barrier.Thus, NOR-gate 152 applies a binary 1 signal to the input of NOR-gate122 in the phase select logic circuit PSL (FIG. 6).

Since NOR-gate 122 has received a binary I signal, it applies a binary0" signal to the input of NOR-gate 128. Since timer T] has timed out, itapplies a binary l signal to input terminal T1 so that NOR-gate 112(FIG. 6) applies a binary 0" signal to one input of NOR-gate 114. Sincewe have not received a select stop signal, the second input of NOR-gate114 also receives a binary 0 signal. Thus, NOR-gate 1 l4 applies abinary 1 signal to NOR-gate 116 which, in turn, applies a binary 0signal to one input of NOR-gate 118. The second input of NOR-gate 118receives a binary 0 signal from the 0 terminal of flip-flop FF-3 whichresulted from receipt of the first trigger pulse from the wave shaperWS. Thus, NOR-gate 118 applies a binary l signal to the input ofNOR-gate 126. Accordingly, both inputs to NOR-gate 128 receive binary 0signals, whereupon this NOR gate applies a binary l signal to the inputof NOR-gate 130. NOR-gate 130 in turn applies a binary 0 signal to theclear terminal C of flip-flop FF-4 which permits this flip-flop to beactuated from one stable state to the other by a negative trailing edgeof a pulse being applied to its trigger terminal T from output terminal1 of flip-flop FF-3.

On the next negative trailing edge of .a pulse from wave shaper WS,flip-flop FF-3 is changed so that its l terminal carries a binary 0signal and its 0 terminal carries a binary 1 signal. This serves totrigger flip-flop FF-4 from its normal stable state condition duringoperation on the left side of the barrier to the condition wherein its1" terminal carries a binary l signal and its 0 terminal carries abinary 0" signal.

At this point, the phase select stop logic circuit SSL (FIG. 9) comparesthe output signals of flip-flops FF-3 and FF-4 along with the signals onoutput circuits a, b, c, and d against the status of detector memoriesAM, BM, CM, and DM. If detector memory CM had been actuated due to aphase C detection, the select stop circuit would produce an outputsignal to prevent further phase select searching operation. However,this is not the case, since only detector memory DM has been soactuated. Accordingly, the searching operation continues; to wit, uponreceipt of another pulse from wave shaper WS, flip-flop FF-3 changes itsstable state so that output circuit l carries a binary l signal andoutput circuit 0" carries a binary 0 signal. Flip-flop FF-4 is notchanged by this operation.

Reference is now made to FIG. 9. Since a detector actuation took placein phase D, a binary 1 signal is present on input terminal DM. Thus,NOR-gate 224 applies a binary 0 signal to one input of NOR-gate 232.Since we are now operating in the right side of the barrier, the loutput terminal of flip-flop FF-4 carries a binary 1 signal. This isinverted by NOR-gate 214 to apply a binary 0 signal to a second input ofNOR-gate 232. Since a binary l signal is present on output terminal l offlip-flop FF-3, NOR-gate 212 applies a binary 0 signal to a third inputof NOR-gate 232. Since we are not yet in the phase D operation, outputcircuit d of the phase select circuit PS is deenergized and carries abinary 0 signal, which is applied to the fourth input of NOR-gate 232.Since all of its inputs carry binary 0" signals, NOR-gate 232 nowapplies a binary 1 signal to the select stop output terminal SS.

Referring now to FIG. 2, since timer Tl had timed out, both inputs toAND-gate 42 carry binary 1" signals. Accordingly, AND-gate 42 applies abinary l signal to the input of NOR- gate in the interval sequencercircuit 15. This causes output circuit g to be deenergized to carry abinary 0 signal, and output circuit y to carry a binary l signal.Accordingly, timer T2 will now commence timing the caution period oftime as adjusted by potentiometer 14 in the phase A timer controlcircuit TC-1. When timer T2 has completed its timing function, itapplies a binary l signal to inputterminal T2 of the phase selectcircuit (FIG. 5

Reference is now made to FIG. 5, from which it will be noted that when abinary 1 signal is applied to input terminal T2, NOR-gate applies abinary 0 signal to one input each of NOR-gates 160,162, 164, 166, and168. The l and 0 terminals of flip-flop FF-3 now respectively carrybinary l and binary 0" signals. Also, the l and 0" terminals offlip-flop FF-4 now respectively carry binary l and binary 0 signals.Accordingly, NOR-gate 164 applies a binary l signal to the input ofNOR-gate 182 in flip-flop FF-S. Thus, through regenerative action,NOR-gate 182 applies a binary 0" signal to the phase on logic circuitand NOR-gate applies 'a binary 1" signal to the phase on logic circuitPOL. Also, NOR-gate 168 applies a binary 1" signal to the input ofNOR-gate 186 in flip-flop FF-6. Accordingly, through regenerativeaction, NOR-gate 184 now applies a binary l" signal to the phase onlogic circuit POL and NOR- gate 186 applies a binary 0" signal to thephase on logic circuit POL. V

As stated hereinbefore, during the description of the same side ofbarrier operation, after timer T2 completes its timing I function, itactuates the inverval sequencer IS so that its output circuit y carriesa binary 0 signal and its output circuit 3 carries a binary l signal.This, in turn, causes timer T2 to be reset, whereupon it applies abinary signal to the input of NOR-gate 170 (FIGS. 3 and 5). Accordingly,NOR-gate 160 now applies a binary 0" signal to the phase on logiccircuit POL. For the same reasons as discussed with respect to the sameside of barrier operation, the outputs of NOR-gates 180, 182, 184, and186 are not changed from that as discussed above.

Reference is now made to FIG. 8. NOR-gate 198 now receives a binary lsignal from the output of NOR-gate 184. Accordingly, NOR-gate 198applies a binary 0 signal to one input of NOR-gate 202. NOR-gate 190receives a binary 0 signal from NOR-gate 160 and a binary 0" signal fromNOR- gate 182. Accordingly, NOR-gate 190 applies a binary 1" signal tothe input of NOR-gate 194. NOR-gate 194, in turn, applies a binary 0"signal to the second input of NOR-gate 202. Accordingly, since both ofits inputs receive binary 0 signals, NOR-gate 202 applies a binary 1"signal to output circuit d. Since output circuit d now carries a binaryl signal and binary 0" signals are now carried by output circuits a, b,and c, the transistor in phase D timer control circuit TC-4 is nowactuated so that a green signal may be displayed to phase D.

SECOND EMBODIMENT Reference is now made to FIGS. 10 and 11, which show asecond form of traffic controller LC-2. Controller LC-2 like controllerLC-l (FIG. 2) is a four phase, full actuated traffic controller. In. theprevious description with respect to controller LC-l, this controllerwas indicated as having a common timing circuit T, four timing controlcircuits TC-l, TC-2, TC-3, and TC-4, and an interval sequencer circuitIS. ControllerL-2, on the other hand, does not include these circuits.Instead, controller LC-2 includes a phase A timer TA, a phase B timerTB, a phase C timer TC, and a phase D timer TD. EAch of these timingcircuits take the form, for example, as shown in FIG. 11 with respect totimer circuit TA. However, controller LC-2 like controller LC-l includesthe phase selection circuit PS, which has alreadybeen described indetail with reference to FIGS. 5, 6, 7, 8, and 9. Controller LC-2 alsoincludes detector memories AM, BM, CM, and DM associated with detectorsDA, DB, DC, and DD. Accordingly, the like components in FIGS. 2 and 10are identified in FIG. 10 with like character references for purposes ofsimplifying the discussion of this aspect of the invention.

It will be noted that the select stop terminal SS of the phase selectcircuit PS is coupled to one input each of timers TA, TB, TC, and TD.Further, each of these timers has an output terminal T1. Terminals T1are commonly connected through diodes 250, 252, 254, and 256 to inputterminal T1 of the phase select circuit PS. Also, each of these timercircuits has an output terminal T2. These output terminals are commonlyconnected through diodes 258, 260, 262, and 264 to input terminal T2 ofthe phase select circuit PS. Further, each of the timer circuits TA, TB,TC, and TD has an output terminal y. Output terminals y are commonlyconnected through diodes 266, 268, 270, and 272 to terminal y of thephase select circuit PS. Also, the phase timers TA, TB, TC, and TD haveoutput terminals g. Output terminals g and y serve the same function asoutput terminals 8 and y of the interval sequencer circuit IS shown inFIG. 2. By making these connections, the phase selection circuit PS willprovide phase selection for a four phase, full actuated controller shownin FIG. 10, as well as for the local controller LC-l describedhereinbefore.

Reference is now made to FIG. 11 which is a schematic illustration ofphase timer TA. The internal circuitry within phase timers TB, TC, andTD is the same as that of phase timer TA. As shown in FIG. 11, the timercircuit TA includes a green timer circuit 280 and a yellow timer circuit282. A NOR-gate 300 is coupled to output circuit a of the phase selectcircuit PS. The output of NOR-gate 300 is applied both to timer circuits280 and 282. In timer circuit 280, the output of NOR-gate 300 is appliedto the input of an NPN-transistor 302 having its emitter connected toground and its collector connected through a resistor 303 to the B+voltage supply source. A capacitor 304 is connected across the emitterto collector circuit of transistor 302. The junction of capacitor 304and resistor 303 is connected to the emitter 308 of a unijunctiontransistor 306. Transistor 306 has its base 52 connected through aresistor 307 to the B+ voltage supply source and its base B1 connectedthrough a resistor 310 to ground. Also, base B1 is connected to theinput of a NOR-gate 312. The output of NOR-gate 312 is connected to theinput of a NOR-gate 314. NOR-gates 312 and 314 are connected together todefine a bistablemultivibrator circuit. A second input to NOR-gate 314is taken from the output of NOR-gate 300. The output of NOR-gate 314 isconnected to output terminal T1 and the output of NOR-gate 312 isconnected to one input of an AND- gate 316. The output of AND-gate 316is connected to output terminal 8 of phase timer TA. The other input toAND-gate 316 is taken from output circuit a of the phase select circuitPS.

One output of NOR-gate 314 is connected to the input of an AND-gate 318.The second input to AND-gate 318 is taken from the select stop terminalSS of the phase select circuit PS.

The output of AND-gate 318 is connected to the input of a NOR-gate 320.

Yellow timer circuit 282 includes. an NPN-transistor 322 having its baseconnected to the output of NOR-gate 320. The emitter of transistor 322is connected to ground and the collector is connected through a resistor323 to a 3+ voltage supply source. A capacitor 324 is connected acrossthe emitter to collector circuit of transistor 324. Also, the junctionof the collector of transistor 322 and capacitor 324 is connected to theemitter 328 of a unijunction transistor 326. This transistor has itsbase Bl connected through a resistor 330 to ground and its base B2connected through a resistor 331 to a B+ voltage supply source. Base B1of transistor 326 is also.

connected to the input of a NOR-gate 332 having its output connected tothe input of a NOR-gate 334. NOR-gates 332 and 334 are connectedtogether to define a two input, bistable multivibrator circuit. A secondinput to NOR-gate 334 is taken from the output of NOR-gate 300. Theoutput of NOR- gate 334 is connected to output terminal T2. AND-gate 336has one input taken from the output of AND- gate 318 and a second inputtaken directly from the output circuit a of the phase select circuit PS.The output of AND-gate 336 is connected to output terminal y. 1

During the operation of controller LC-2, the phase select circuit PSwill, in the fashion as described hereinbefore with reference to FIGS.5, 6, 7, 8, and 9, select different phase timers for operation. Thus,when output circuit a of phase select circuit PS carries a binary lsignal, NOR-gate 300 applies a binary 0 signal to the base of transistor302. This reverse biases transistor 302 and permits capacitor 304 tocharge towards the 13+ potential. When the voltage level stored by thecapacitor exceeds the peak point voltage of the unijunction transistor306, the capacitor discharges through the emitter 308 to the base 81terminal and thence through load resistor 310 to ground. This positivepotential developed across load resistor 310 serves as a binary l signalfor application to the input of NOR-gate 312. Thus, the output ofNOR-gate 312 applies a binary 0 signal to the input of NOR-gate 314.Since the output of NOR-gate 300 is also a binary 0? signal, both inputsto NOR-gate 314 carry binary 0" signals. Accordingly, NOR-gate 314applies a binary l" signal to output terminal T1 and a binary 1" signalto one input of AND-gate 318. During the period that capacitor 304 ischarging to time the green period of time, NOR-gate 312 applies a binaryl signal to one input of AND-gate 316. The other input to AND-gate 316is taken from output circuit A of the phase select circuit. Accordingly,AND-gate 316 applies a binary l signal to its output circuit 3 duringthe period that capacitor 304 is charging.

When the green timer has completed its timing function and applies abinary l signal to its output terminal T1, this signal is in turnapplied to input terminal T1 of the phase select circuit PS. This causesthe phase select circuit to commence its searching operations todetermine if another phase is traffic actuated. This operation is thesame as has been discussed hereinbefore with reference to FIGS. 5, 6, 7,8, and 9, and no further description is deemed necessary for a completeunderstanding of this operation. Once this phase select circuit PS hascompleted its searching function and has found a calling phase, itapplies a binary l signal from its select stop output terminal SS to thesecond input of AND-gate 318 (FIG. 11). Thus, AND-gate 318 applies abinary 1 signal to the input of NOR-gate 320 as well as to one input ofAND-gate 336. Since the second input of AND-gate 336 is connected tooutput circuit a of the phase select circuit PS AND-gate 336 applies abinary l signal to its output circuit y. NOR-gate 320 now applies abinary signal to the input of NPN-transistor 322. This reverse biasestransistor 322 to permit capacitor 324 to charge toward the B+potential. When the voltage stored by capacitor 324 exceeds the peakpoint voltage of unijunction transistor 326, the capacitor dischargesthrough the emitter 328 and base B1 and thence through load resistor 330to ground. This serves as a positive or binary l signal for applicationto the input of NOR-gate 332. Thus, the output of NOR-gate 334 nowcarries a binary 1 signal which is applied to output terminal T2 forapplication to input terminal T2 in the phase select circuit PS. As wasdescribed hereinbefore, once a binary 1 signal is applied to inputterminal T2 of the phase select circuit PS, the information stored inthe phase select search circuit PS8 is shifted to flip-flops FF-S andFF-6 (FIG. It will be recalled from the previous description withreference to FIG. 5, that a second signal in the form of a binary 0"signal was applied to input terminal T2. The only effect had on thatcircuit in FIG. 5 is the change of the output of NOR-gate 160 from abinary 1 signal to a binary 0" signal. Accordingly, for the embodimentshown in FIGS. 10 and 11, NOR-gate 160 in FIG. 5 may be short circuitedin order to complete the shifting operation. Once the phase selectcircuit PSS completed its phase selection operation, output circuit A isdeenergized to carry a binary 0 signal. Thus, with reference to FIG. 11,NOR-gate 300 applies a binary l signal to NOR-gates 314 and 334 to resetthe timer circuits 280 and 282, whereupon output terminals T1 and T2carry binary O signals. The remaining aspects of the phase selectionoperation of phase select circuit PS used in conjunction with a trafficcontroller of the nature described with reference to FIGS. 10 and 11 isthe same as has been described previously with reference to localcontroller LC-l.

PREEMPTION CONTROL Reference is now made to FIG. 12 which shows thepreemption control circuit. This circuit may be used with the four phasecontroller shown in FIGS. 10 and 11 and, preferably, with the four phasecontroller shown in FIG. 2. The preemption control circuit serves thepurpose of placing the controller in a particular point in its cycle ofoperation as dictated by the condition of program switches S1, S2, S3.Whenever a preemption signal occurs, represented by a closure switch S0,the preemption control circuit automatically forces the controller intothe programmed operation. This operation is desirable, for example,during a fire lane emergency situation. Another use of the preemptioncontrol circuit is when a railroad crosses one of the approaches to anintersection and, hence, upon detection of a train crossing thatapproach, a preemption control program is placed into effect.

The preemption control circuit serves to control the outputs offlip-flops FF5 and FF-6 (see FIG. 5) as well as the interval sequencerflip-flop IS (see FIG. 2). As has been described previously with respectto the description of operation regarding phase selection, the output ofNOR gate 180 in flip-flop F F-S serves as the phase on right circuit andis coupled to the input of NOR gate in the phase on logic circuit POI...Similarly, the output of NOR-gate 182 serves as the phase on leftcircuit and is coupled to the input of NOR-gate 192 in the phase onlogic circuit POL. The output of NOR-gate 184 in flip-flop FF-6 servesas the phase on barrier right circuit and is coupled to the input of NORgate 198 in the phase on logic circuit POL. Similarly, the output ofNOR-gate 186 serves as the phase on barrier left circuit and isconnected to the input of NOR-gate 200 in the phase on logic circuitPOL. The output circuits of NOR-gates 80, 82 in the interval sequencercircuit IS are respectively connected to output circuits g and y. Thenature of the binary signals carried by these output circuits determinesthe status of the controller when operating power is turned on. Thus, ifthe phase on right output circuit, the phase on barrier right outputcircuit, and output circuit g each carry' binary 1 signals, then phase Dis allocated a green signal.

The preemption control circuit includes preemption control switch S0which, as shown in FIG. 12, is represented as a normally open switch. Itis to be appreciated, of course, that switches S0, S1, S2, and S3 maytake the form of solid state switches, such as transistors. Switch S0,for example, may be a transistor controlled by a remote circuit during afire lane emergency situation or by a detector for detecting a railroadcrossing situation. The preemption control circuit includes NOR-gates500, 504, 506, 508, 510, and 512. Each of these NOR gates has one inputconnected through normally open switch S0 to ground as well as through aresistor 514 to the B+ voltage supply source. The outputs of NOR-gates500, 504, 506, 508, 510, and 512 are respectively coupled to the inputsof NOR-gates 180, 182, 184, 186, 80, and 82. The second input ofNOR-gate 500 is coupled through a resistor 516 to a 8+ voltage supplysource as well as through a normally open program switch S1 to ground.NOR-gate 518 has its input connected to the junction of resistor 516 andswitch S1 and its output connected to the second input of NOR-gate 504.NOR- gate 506 has its second input connected through a resistor 520, toa 8+ voltage supply source, as well as through normally open programswitch S2 to ground. A NOR-gate 522 has its input connected to thejunction of switch S2 and resistor 520, and its output connected to thesecond input of NOR- gate 508. NOR-gate 510 has its second inputconnected through a resistor 524 to a B+ voltage supply source as wellas through normally open program switch S3 to groundpA NOR- gate 526 hasits input connected to the junction of switch S3 and resistor 524, andits output connected to the second input of NOR-gate 512.

Program switch S1 serves to control whether the phase on right outputcircuit or phase on left output circuit will be energized to carry abinary l signal. If the switch is closed, then upon closure of switch S0the phase on left circuit carries a binary l" signal. If the switch isopen, then the phase on right circuit will carry a binary l signal, onceswitch S0 has been closed. Similarly, switch S2 serves when closed toplace a binary l" signal on the phase on barrier left circuit and whenopen to provide a binary 0" signal to the phase on barrier rightcircuit, once switch S0 is closed. Also, switch S3 serves when closed toplace a binary 1" signal on output circuit y and when open to place abinary l signal on output circuit g, once switch S0 has been closed.

' Assume that it is desired that once switch S0 is closed the controllerwill provide a yellow signal on phase D. If so, then since phase D is onthe right side of tI-Ie barrier switch S2 is opened. Also, since phase Dis on the right side of the right barrier, switch S1 is opened. However,since we desire to have a yellow signal displayed to phase D, switch S3is closed. Accordingly, once switch S0 becomes closed, a binary 0"signal is applied to one input of each of the NOR-gates 500, 504, 506,508, 510, and 512. Since switch S3 is closed, a binary 0 signal isapplied to the second input of NOR-gate 510 and to the input of NOR-gate526. NOR-gate 526, in turn, applies a binary l signal to the input ofNOR-gate 512.-Since one of its inputs carry a binary 1" signal, NOR-gate512 applies a binary signal to NOR-gate 82. On the other hand, sinceboth of its inputs receive binary 0" signals, NOR-gate 510 applies abinary l signal to the input of NOR-gate 80. Through regenerativeaction, output circuit y of interval sequencer circuit IS carries abinary l signal and output circuit 3 carries a binary 0" signal. Sinceswitch S1 is open, the second input to NOR-gate 500 receives a binary lsignal and, hence, NOR- gate 500 applies a binary 0" signal to the inputof NOR-gate 180. However, both inputs of NOR-gate 504 receive binary 0"signals whereupon this NOR gate applies a binary 1 signal to the inputof NOR-gate 182. Through regenerative action, NOR-gate 180 applies abinary l signal to the phase on right output circuit and a binary 0signal to the phase on left output circuit. Since switch S2 is open, oneof the inputs to NOR-gate 506 is a binary "1 signal and, accordingly,NOR- gate 506 applies a binary 0" signal to the input of NOR-gate 184.However, both of the inputs of NOR-gate 508 receive binary 0 signals,whereupon NOR-gate 508 applies a binary l signal to the-input ofNOR-gate 186. Through regenerative action, NOR-gate 184 applies a binary1" signal to the phase on barrier right circuit, and a binary 0" signalto the phase on barrier left circuit. Since binary l signals are nowcarried by the phase on right circuit, the phase on barrier rightcircuit and output circuit y is indicative of a yellow signal to beallocated to phase D. Accordingly, this program of switches S0, S1, S2,and S3 will force the controller to display a yellow signal to phase Dwhen switch S0 is closed.

ORIENTATION PROGRAMMING CIRCUIT Reference is now made to FIG. 13 whichschematically illustrates the orientation programming circuitry. Thiscircuitry, but for the inclusion of NOR-gate 530 having its inputconnected to normally open switch S0, is essentially the same as thepreemption control circuit described previously with reference to FIG.12. The output of NOR-gate 530 is connected to one input each ofNOR-gates 44, 52, 60, and 70, respectively, located in the detectormemories AM, BM, CM, and DM (FIG. 2).

The purpose of this circuitry is that upon each closure of thepreemption, or in this case the orientation, switch $0, a binary 0"signal is applied to the input of NOR-gate 530. NOR-gate 530, in turn,applies a binary l signal to one input each of NOR-gates 44, 52, 60, and70. This simulates a traffic detection having taken place in each of thetraffic phases A, B, C, and D. One application of this circuit is thatwhen power has failed and has been re-established, each of the phaseswill sequentially receive traffic signals. In the absence of thisfeature, when power is returned the controller would display signals inaccordance with the positioning of program switches S1, S2, and S3.Since many intersections use spot detectors, as opposed to presencedetectors, a traffic detection may not be noted by the controller whenpower is lost and then returned. Accordingly, a vehicle that hadactuated the spot detector and is now awaiting a right-of-way signalmust backup to reactuate the spot detector. To prevent this, NOR-gate530 serves, upon each closure of switch S0, to simulate a trafficdetection on all traffic phases. Thus, when power is returned, thecontroller will cycle once in a sequential fashion to present go trafficsignals in phases A, B, C, and D.

Although the invention has been described in connection with preferredembodiments, it will be readily apparent to those skilled in the artthat various changes in form and arrangement of parts may be made tosuit requirements without departing from the spirit and scope of theinvention as defined by the appended claims.

We claim:

1. In a trafiic control system for controlling the operation of atrafiic signal means displaying traffic signals including a go signalfor each of at least three traffic phases, and wherein signal means forat least two of said phases are responsive to traffic having trafficdetection means associated therewith for detecting traffic controlled bythe signal means associated with such traffic detector; the improvementfor transferring go signal activation from one of said phases to a phaseassociated with traffic detection means which has detected traffic,wherein said system comprises:

separate means for each phase for controlling activation of a go signalduring that phase; calling means for each such phase for providing acalling signal representative that traffic detection means of theassociated phase is traffic activated;

a source of trigger pulses;

phase select counting means for counting said trigger pulses, saidcounting means having a plurality of output circuits which carry apattern of output signals that changes in dependence upon the number oftrigger pulses counted, said pattern of output signals beingrepresentative, at any one time, of conditions in a thoroughfareassociated with one of said phases;

logic comparison means for comparing said pattern of output signals withsaid calling signals for providing a comparison'signal when the saidpattern of output signals is representative of the condition of the samethoroughfare that is represented by a said calling signal; and,

phase on activating means for activating the separate activatable meansfor the said same phase to control allocation of a go signal activationthereto, whereby a said go signal activation is directly transferredfrom one of said phases to another of said phases for which thedetection means is actuated.

2. In a traffic control system as set forth in claim 1, count controlmeans responsive to a said comparison signal to prevent said countingmeans from counting additional said trigger pulses.

3. In a traffic control system as set forth in claim 1, signal shiftingmeans interposed between the output circuits of said counting means andsaid phase on activating means for applying signals to said phase onactivating means representative of the pattern of output signals on theoutput circuits of said counting means when the last said comparisonsignal was provided.

4. In a traffic control system as set forth in claim 3, the improvementwherein said phase on activating means has a plurality of outputcircuits each coupled to one of said separate means for applying a phaseon signal thereto for activating same and decoding means for decodingsaid representative signals and placing a said phase on signal on thedecoder output circuit that is coupled to the separate means for thephase corresponding with that represented by the last pattern of outputsignals on the counting means output circuits.

5. In a traffic control system as set forth in claim 1, orientationprogramming means for activating each said calling means so that eachsaid calling means provides a said calling signal.

6. In a traffic control system as set forth in claim 1, preemptioncontrol means for activating said phase on activating means to actuate apreselected one of said separate means.

7. In a traffic control system as set forth in claim 3, the improvementwherein said signal shifting means includes memory means having aplurality of input circuits coupled to the outputs of said phase selectcounting means and a plurality of output circuits coupled to said phaseon activating means; shift logic means interposed between said phaseselect counting means and said memory means for applying signals to saidmemory means input circuits whereupon the output circuits of said memorymeans apply said representative signals to said phase on activatingmeans.

8. In a traffic control system as set forthin claim 7, means foractivating said shift logic means.

9. In a traffic control system as set forth in claim 7, preemptioncontrol circuit means coupled to the input circuis of said memory meansfor activating same so that said memory means output circuits carry apreselected pattern of signals, whereby said phase on activating meansactivates a preselected one of said separate means.

1. In a traffic control system for controlling the operation of atraffic signal means displaying traffic signals including a go signalfor each of at least three traffic phases, and wherein signal means forat least two of said phases are responsive to traffic having trafficdetection means associated therewith for detecting traffic controlled bythe signal means associated with such traffic detector; the improvementfor transferring go signal activation from one of said phases to a phaseassociated with traffic detection means which has detected traffic,wherein said system comprises: separate means for each phase forcontrolling activation of a go signal during that phase; callinG meansfor each such phase for providing a calling signal representative thattraffic detection means of the associated phase is traffic activated; asource of trigger pulses; phase select counting means for counting saidtrigger pulses, said counting means having a plurality of outputcircuits which carry a pattern of output signals that changes independence upon the number of trigger pulses counted, said pattern ofoutput signals being representative, at any one time, of conditions in athoroughfare associated with one of said phases; logic comparison meansfor comparing said pattern of output signals with said calling signalsfor providing a comparison signal when the said pattern of outputsignals is representative of the condition of the same thoroughfare thatis represented by a said calling signal; and, phase on activating meansfor activating the separate activatable means for the said same phase tocontrol allocation of a go signal activation thereto, whereby a said gosignal activation is directly transferred from one of said phases toanother of said phases for which the detection means is actuated.
 2. Ina traffic control system as set forth in claim 1, count control meansresponsive to a said comparison signal to prevent said counting meansfrom counting additional said trigger pulses.
 3. In a traffic controlsystem as set forth in claim 1, signal shifting means interposed betweenthe output circuits of said counting means and said phase on activatingmeans for applying signals to said phase on activating meansrepresentative of the pattern of output signals on the output circuitsof said counting means when the last said comparison signal wasprovided.
 4. In a traffic control system as set forth in claim 3, theimprovement wherein said phase on activating means has a plurality ofoutput circuits each coupled to one of said separate means for applyinga phase on signal thereto for activating same and decoding means fordecoding said representative signals and placing a said phase on signalon the decoder output circuit that is coupled to the separate means forthe phase corresponding with that represented by the last pattern ofoutput signals on the counting means output circuits.
 5. In a trafficcontrol system as set forth in claim 1, orientation programming meansfor activating each said calling means so that each said calling meansprovides a said calling signal.
 6. In a traffic control system as setforth in claim 1, preemption control means for activating said phase onactivating means to actuate a preselected one of said separate means. 7.In a traffic control system as set forth in claim 3, the improvementwherein said signal shifting means includes memory means having aplurality of input circuits coupled to the outputs of said phase selectcounting means and a plurality of output circuits coupled to said phaseon activating means; shift logic means interposed between said phaseselect counting means and said memory means for applying signals to saidmemory means input circuits whereupon the output circuits of said memorymeans apply said representative signals to said phase on activatingmeans.
 8. In a traffic control system as set forth in claim 7, means foractivating said shift logic means.
 9. In a traffic control system as setforth in claim 7, preemption control circuit means coupled to the inputcircuits of said memory means for activating same so that said memorymeans output circuits carry a preselected pattern of signals, wherebysaid phase on activating means activates a preselected one of saidseparate means.
 10. In a traffic controller for controlling theoperation of signal light means displaying traffic signals including ago signal for each of at least three traffic phases, and wherein controlfor at least two of said phases is traffic activatable having trafficdetection means associated therewith for detecting traffic inthoroughfares associated with such phases; the improvement comprisinG: acommon timer circuit associated with all of said phases and having a gotiming means for timing a go interval; timer control circuit means foreach phase for controlling the duration said go timing means times a gointerval; and phase selection means for activating a said timer controlcircuit means associated with one of said phases for which detectionmeans has been actuated, whereby a said go signal activation is directlytransferred from one of said phases to the phase for which detectionmeans has been actuated.
 11. In a traffic controller as set forth inclaim 10, calling means for each activatable phase for providing acalling signal representative that the associated phase is trafficactivated.
 12. In a traffic controller as set forth in claim 11, theimprovement wherein said phase selection means includes: a source oftrigger pulses; and phase select counting means for counting saidtrigger pulses, said counting means having a plurality of outputcircuits which carry a pattern of output signals that changes independence upon the number of trigger pulses counted, said pattern ofoutput signals being representative, at any one time, of a particularone of said phases.
 13. In a traffic controller as set forth in claim 11logic comparison means for comparing said pattern of output signals withsaid calling signals for providing a comparison signal when said patternof output signals is representative of the same activated phase that isrepresented by a said calling signal.
 14. In a traffic controller as setforth in claim 13, phase on activating means for activating the timercontrol circuit means for the said phase represented by the last saidpattern of output signals on the counting means output circuits.
 15. Ina traffic controller as set forth in claim 14, count control meansresponsive to a said comparison signal for preventing said countingmeans from counting additional said trigger pulses.
 16. In a trafficcontroller as set forth in claim 14, signal shifting means interposedbetween the output circuits of said counting means and said phase onactivating means for applying signals to said phase on activating meansrepresentative of the pattern of output signals on the output circuitsof said counting means when the last said comparison signal wasprovided.
 17. In a traffic controller as set forth in claim 16, theimprovement wherein said phase on activating means has a plurality ofoutput circuits each coupled to an associated one of said timer controlcircuit means for applying a phase on signal thereto activating, anddecoding means for decoding said representative signals and placing asaid phase on signal on the phase on output circuit that is coupled tothe timer control circuit means for the phase corresponding with thephase represented by the last pattern of output signals on the countingmeans output circuits.
 18. In a traffic controller as set forth in claim11, orientation programming means for activating each said calling meansso that each said calling means provides a said calling signalrepresentative that the associated phase is traffic activated.
 19. In atraffic controller as set forth in claim 14, including preemptioncontrol means for activating said phase on activating means to activatea preselected one of said timer control circuit means.